Essential Misses and Data Traffic in Coherence Protocols

In this paper we introduce a classification of misses and of components of the data traffic in shared-memory multiprocessors based on inter-processor communication. We consider protocols with invalidations, updates and prefetches in systems with infinite and finite caches. We identify the set of essential misses and the essential traffic, i.e., the smallest set of misses and the smallest amount of traffic necessary for correct execution. The rest of the misses and of the data traffic is non-essential and could be ignored without affecting the correctness of program execution. To illustrate the classification of misses and traffic, we apply it to a set of parallel scientific programs and observe the overhead created by different hardware mechanisms when block sizes and cache sizes are varied.